首页 \ 问答 \ 8位阵列乘法器VHDL（输出错误）(8 bits Array Multiplier VHDL (output wrong))

8位阵列乘法器VHDL（输出错误）(8 bits Array Multiplier VHDL (output wrong))

 我正在尝试用VHDL制作一个8位数组乘法器，我使用数组乘法器的标准架构来做到这一点，我有一个接收A（被乘数）和B（乘数）的BDF文件，并且在这个BDF文件中有一个名为“adder”的块，它从A和B的乘积中得到总和。我遇到了和输出的问题，它显示的数字远低于正确的值。 在此处输入图像描述 
 

 上面的图片是我的主要BDF。 
 

 在此处输入图像描述 
 

 上图显示了从and_arrays到加法器的de连接。 
 

 加法器代码： 
 

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
use IEEE.std_logic_arith.ALL;
use IEEE.numeric_std.ALL;

ENTITY adder IS
  PORT (i_IN0   : IN  STD_LOGIC_VECTOR(7 downto 0);-- data input
        i_IN1   : IN  STD_LOGIC_VECTOR(7 downto 0);-- data input
        i_IN2   : IN  STD_LOGIC_VECTOR(7 downto 0);-- data input
        i_IN3   : IN  STD_LOGIC_VECTOR(7 downto 0);-- data input
        i_IN4   : IN  STD_LOGIC_VECTOR(7 downto 0);-- data input
        i_IN5   : IN  STD_LOGIC_VECTOR(7 downto 0);-- data input
        i_IN6   : IN  STD_LOGIC_VECTOR(7 downto 0);-- data input
        i_IN7   : IN  STD_LOGIC_VECTOR(7 downto 0);-- data input
        o_Q     : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
        o_COUT  : OUT STD_LOGIC);-- data output  
END adder;

architecture arch1 of adder is 
begin 
    process(i_IN0, i_IN1, i_IN2, i_IN3, i_IN4, i_IN5, i_IN6, i_IN7)
      variable soma:std_logic_vector(14 downto 0);
      variable aux0:std_logic_vector(14 downto 0);
      variable aux1:std_logic_vector(14 downto 0);
      variable aux2:std_logic_vector(14 downto 0);
      variable aux3:std_logic_vector(14 downto 0);
      variable aux4:std_logic_vector(14 downto 0);
      variable aux5:std_logic_vector(14 downto 0);
      variable aux6:std_logic_vector(14 downto 0);
      variable aux7:std_logic_vector(14 downto 0);
      variable c:std_logic; -- carry in
      BEGIN
         aux0(7 downto 0) := i_IN0; aux0(14 downto 8) := "0000000"; -- here i'm trying to shift the 8 nbit input value
         aux1(0) := '0'; aux1(8 downto 1) := i_IN1; aux1(14 downto 9) := "000000"; -- to a 15 bit value to the sums
         aux2(1 downto 0) := "00";aux2(9 downto 2) := i_IN2; aux2(14 downto 10) := "00000"; -- looking to the array multiplier
         aux3(2 downto 0) := "000";aux3(10 downto 3) := i_IN3; aux3(14 downto 11) := "0000"; -- architecture, it seem to be
         aux4(3 downto 0) := "0000";aux4(11 downto 4) := i_IN4; aux4(14 downto 12) := "000"; -- correct
         aux5(4 downto 0) := "00000";aux5(12 downto 5) := i_IN5; aux5(14 downto 13) := "00";
         aux6(5 downto 0) := "000000"; aux6(13 downto 6) := i_IN6; aux6(14) := '0';
         aux7(6 downto 0) := "0000000"; aux7(14 downto 7) := i_IN7;
    -- below the loop that make the sums bit-in-bit, i've addapted this code from a 8 bit adder
         c := '0';
            for i in 0 to 14 loop
                soma(i) := aux0(1) xor aux1(i) xor aux2(i) xor aux3(i) xor aux4(i) xor aux5(i) xor aux6(i) xor aux7(i) xor c;
                c := (aux0(i) and aux1(i) and aux2(i) and aux3(i) and aux4(i) and aux5(i) and aux6(i) and aux7(i)) or ((aux0(i) xor aux1(i) xor aux2(i) xor aux3(i) xor aux4(i) xor aux5(i) xor aux6(i) xor aux7(i)) and c);
            end loop;
            o_COUT <= c; 
            o_Q(15) <= c; -- carry out atribuition to the last bit of the vector
            o_Q(14 downto 0) <= soma;
    end process;
end arch1;

 

 和阵列代码： 
 

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
use IEEE.std_logic_arith.ALL;

ENTITY and_array IS
  PORT (i_MULTIPLICANDO   : IN  STD_LOGIC_VECTOR(7 downto 0);-- data input
        i_MULTIPLICADOR   : IN  STD_LOGIC;-- data input
        o_Q   : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));-- data output
END and_array;

ARCHITECTURE arch_1 OF and_array IS
    BEGIN
        GEN_REG: 
        FOR i IN 0 TO 7 GENERATE
            o_Q(i) <= i_MULTIPLICADOR and i_MULTIPLICANDO(i); 
        END GENERATE GEN_REG;
END arch_1;

 

 我已经为这两个块进行了模拟，并且数组块完美地工作，但是错误出现在加法器模拟中，在模拟的图像下面： 
 

 在此处输入图像描述 
 

 我正在模拟以下输入： 
 

        Multiplicand = 1 1 1 1 0 1 0 1 (245 dec)
        Multiplier   = 1 0 1 0 1 1 1 1 (175 dec)

 

 该产品的正确值为42785，在我的模拟中显示为24899 
 

 我在加法器中使用以下逻辑： 
 

                   1 1 1 1 0 1 0 1
                   1 0 1 0 1 1 1 1
                   -----------------
      x x x x x x x 1 1 1 1 0 1 0 1     p1
      x x x x x x 1 1 1 1 0 1 0 1 x     p2
      x x x x x 1 1 1 1 0 1 0 1 x x     p3
      x x x x 1 1 1 1 0 1 0 1 x x x     p4 
      x x x 0 0 0 0 0 0 0 0 x x x x     p5
      x x 1 1 1 1 0 1 0 1 x x x x x     p6
      x 0 0 0 0 0 0 0 0 x x x x x x     p7
      1 0 1 0 1 1 1 1 x x x x x x x     p8
_________________________________________

 

 在加法器块中，我将0的所有“X”改为总和（像移位一样）。 在加法器块的循环中，p1到p8的总和是bit-in-bit。 可能是这个循环或进位中的错误，但我试图从多种形式做到这一点并且总是出错。 
 

 有人知道如何解决这个问题吗？ 
 

 下面是主电路抽象图像： 
 

 在此处输入图像描述 

I'm trying to make a 8 bits Array Multiplier in VHDL, I am using the standard architecture of the array multiplier to do this, i have a BDF file receiving the A(multiplicand) and B(multiplier), and in this BDF file have a block named "adder" that makes the sums from the products of A and B. I'm having problems with the sum output, its showing a much lower number from the correct value. enter image description here
 

The image above is my main BDF.
 

enter image description here
 

The image above shows de connections from and_arrays to the adder.
 

Adder code:
 

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
use IEEE.std_logic_arith.ALL;
use IEEE.numeric_std.ALL;

ENTITY adder IS
  PORT (i_IN0   : IN  STD_LOGIC_VECTOR(7 downto 0);-- data input
        i_IN1   : IN  STD_LOGIC_VECTOR(7 downto 0);-- data input
        i_IN2   : IN  STD_LOGIC_VECTOR(7 downto 0);-- data input
        i_IN3   : IN  STD_LOGIC_VECTOR(7 downto 0);-- data input
        i_IN4   : IN  STD_LOGIC_VECTOR(7 downto 0);-- data input
        i_IN5   : IN  STD_LOGIC_VECTOR(7 downto 0);-- data input
        i_IN6   : IN  STD_LOGIC_VECTOR(7 downto 0);-- data input
        i_IN7   : IN  STD_LOGIC_VECTOR(7 downto 0);-- data input
        o_Q     : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
        o_COUT  : OUT STD_LOGIC);-- data output  
END adder;

architecture arch1 of adder is 
begin 
    process(i_IN0, i_IN1, i_IN2, i_IN3, i_IN4, i_IN5, i_IN6, i_IN7)
      variable soma:std_logic_vector(14 downto 0);
      variable aux0:std_logic_vector(14 downto 0);
      variable aux1:std_logic_vector(14 downto 0);
      variable aux2:std_logic_vector(14 downto 0);
      variable aux3:std_logic_vector(14 downto 0);
      variable aux4:std_logic_vector(14 downto 0);
      variable aux5:std_logic_vector(14 downto 0);
      variable aux6:std_logic_vector(14 downto 0);
      variable aux7:std_logic_vector(14 downto 0);
      variable c:std_logic; -- carry in
      BEGIN
         aux0(7 downto 0) := i_IN0; aux0(14 downto 8) := "0000000"; -- here i'm trying to shift the 8 nbit input value
         aux1(0) := '0'; aux1(8 downto 1) := i_IN1; aux1(14 downto 9) := "000000"; -- to a 15 bit value to the sums
         aux2(1 downto 0) := "00";aux2(9 downto 2) := i_IN2; aux2(14 downto 10) := "00000"; -- looking to the array multiplier
         aux3(2 downto 0) := "000";aux3(10 downto 3) := i_IN3; aux3(14 downto 11) := "0000"; -- architecture, it seem to be
         aux4(3 downto 0) := "0000";aux4(11 downto 4) := i_IN4; aux4(14 downto 12) := "000"; -- correct
         aux5(4 downto 0) := "00000";aux5(12 downto 5) := i_IN5; aux5(14 downto 13) := "00";
         aux6(5 downto 0) := "000000"; aux6(13 downto 6) := i_IN6; aux6(14) := '0';
         aux7(6 downto 0) := "0000000"; aux7(14 downto 7) := i_IN7;
    -- below the loop that make the sums bit-in-bit, i've addapted this code from a 8 bit adder
         c := '0';
            for i in 0 to 14 loop
                soma(i) := aux0(1) xor aux1(i) xor aux2(i) xor aux3(i) xor aux4(i) xor aux5(i) xor aux6(i) xor aux7(i) xor c;
                c := (aux0(i) and aux1(i) and aux2(i) and aux3(i) and aux4(i) and aux5(i) and aux6(i) and aux7(i)) or ((aux0(i) xor aux1(i) xor aux2(i) xor aux3(i) xor aux4(i) xor aux5(i) xor aux6(i) xor aux7(i)) and c);
            end loop;
            o_COUT <= c; 
            o_Q(15) <= c; -- carry out atribuition to the last bit of the vector
            o_Q(14 downto 0) <= soma;
    end process;
end arch1;

 

AND ARRAY CODE:
 

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
use IEEE.std_logic_arith.ALL;

ENTITY and_array IS
  PORT (i_MULTIPLICANDO   : IN  STD_LOGIC_VECTOR(7 downto 0);-- data input
        i_MULTIPLICADOR   : IN  STD_LOGIC;-- data input
        o_Q   : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));-- data output
END and_array;

ARCHITECTURE arch_1 OF and_array IS
    BEGIN
        GEN_REG: 
        FOR i IN 0 TO 7 GENERATE
            o_Q(i) <= i_MULTIPLICADOR and i_MULTIPLICANDO(i); 
        END GENERATE GEN_REG;
END arch_1;

 

I've made simulation for this two blocks, the and array blocks works perfectly, but the error appears in the adder simulation, below the imagem from the simulation:
 

enter image description here
 

I'am simulating the following inputs:
 

        Multiplicand = 1 1 1 1 0 1 0 1 (245 dec)
        Multiplier   = 1 0 1 0 1 1 1 1 (175 dec)

 

The correct value for this product is 42785, in my simulation appears 24899
 

I am using the following logic to the sums in adder:
 

                   1 1 1 1 0 1 0 1
                   1 0 1 0 1 1 1 1
                   -----------------
      x x x x x x x 1 1 1 1 0 1 0 1     p1
      x x x x x x 1 1 1 1 0 1 0 1 x     p2
      x x x x x 1 1 1 1 0 1 0 1 x x     p3
      x x x x 1 1 1 1 0 1 0 1 x x x     p4 
      x x x 0 0 0 0 0 0 0 0 x x x x     p5
      x x 1 1 1 1 0 1 0 1 x x x x x     p6
      x 0 0 0 0 0 0 0 0 x x x x x x     p7
      1 0 1 0 1 1 1 1 x x x x x x x     p8
_________________________________________

 

In the adder block i've changed all the "X's" for 0 to the sum (Like a shift). In the loop of the adder block the sums of p1 to p8, is made bit-in-bit. Probably the error it's in this loop or in the carry, but i've tried to do this from many forms and always goes wrong.
 

Someone have any idea how to fix this?
 

Below it's the main circuit abstraction image:
 

enter image description here

原文：https://stackoverflow.com/questions/37601027
更新时间：2023-09-24 12:09

最满意答案

 您的查询正在执行不同的操作。 LINQ-to-Entities查询中的一些问题： 
 

     
 
  1.  您调用Include(...) ，它将急切地为db.Posts每个项目加载User 。 
    2.  
 
  2.  您为每个组中的每个记录调用Count() 。 这可以重写，以便每组只记录一次记录。 
    3.  
 
  3.  最大的问题是您只使用User对象的Name属性。 您可以只选择此字段并找到相同的结果。 选择，分组和返回150万字符串应该是EF中的快速操作。 
    4.  

 

 原版的： 
 

var results = 
    db.Posts
      .Include(u => u.User)
      .GroupBy(g => g.User)
      .Select(g => new { Nick = g.Key.Name, Count = g.Count() })
      .OrderByDescending(e => e.Count)
      .ToList();

 

 建议： 
 

var results = 
    db.Posts
      .Select(x => x.User.Name)
      .GroupBy(x => x)
      .Select(x => new { Name = x.Key, Count = x.Count() })
      .OrderByDescending(x => x.Count)
      .ToList();

 

 如果EF核心仍然对它允许的分组语句类型有限制，则可以在第一个Select(...)语句之后调用ToList 。 

Your queries are doing different things. Some issues in your LINQ-to-Entities query:
 

     
 
  1. You call Include(...) which will eagerly load the User for every item in db.Posts. 
    2.  
 
  2. You call Count() for each record in each group. This could be rewritten to count the records only once per group.
    3.  
 
  3. The biggest issue is that you're only using the Name property of the User object. You could select just this field and find the same result. Selecting, grouping, and returning 1.5 million strings should be a fast operation in EF.
    4.  

 

Original:
 

var results = 
    db.Posts
      .Include(u => u.User)
      .GroupBy(g => g.User)
      .Select(g => new { Nick = g.Key.Name, Count = g.Count() })
      .OrderByDescending(e => e.Count)
      .ToList();

 

Suggestion:
 

var results = 
    db.Posts
      .Select(x => x.User.Name)
      .GroupBy(x => x)
      .Select(x => new { Name = x.Key, Count = x.Count() })
      .OrderByDescending(x => x.Count)
      .ToList();

 

If EF core still has restrictions on the types of grouping statements it allows, you could call ToList after the first Select(...) statement.

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