弹簧与反应堆结合(spring integration sftp with reactor)

 门级仿真包括设计原语的时序，例如触发器，因此必须遵守数据到触发器的建立和保持时间，否则触发器可能在输出上产生“X”。 
 
 测试台代码不是用这个写的; 例如： 
 
wait until clk ='1';
reset <= '0';
 
 在clk上升沿之后0 ps移除reset ，并且取决于实现，可能存在同步设计reset保持时间要求。 
 
 这可以通过以“慢”时钟运行来解决，并且仅从上升的clk边缘“远”改变数据。 这是可以接受的，因为设计时序应该通过静态时序分析（STA）验证，而不是模拟; 后综合模拟只是为了让人感觉设计没问题，但通过测试用例验证设计时序是不现实的。 
 
 您也可以考虑将这些过程编写为时钟过程或组合过程，因为这通常会使设计更容易编写，读取和调试。 calc过程是在clk上升沿和calcstate上更新的过程的示例。 

Gate-level simulation includes timing for design primitives, for example flip-flops, so setup and hold time for data to flip-flops must be respected, and otherwise the flip-flops may generate 'X' on the output.
 
The test bench code is not written with this in mind; for example:
 
wait until clk ='1';
reset <= '0';
 
The reset is removed 0 ps after rising edge of clk, and depending on the implementation there may be hold-time requirement for the synchronous design reset.
 
This can be addressed by running at a "slow" clock and only change data "far" from the rising clk edge. This is acceptable since design timing should be verified through Static Timing Analysis (STA) and not simulation; post-synthesis simulation is only to get a good feeling that the design is OK, but it is unrealistic to verify design timing through test cases.
 
You may also consider writing the processes as either clocked process or combinatorial process, since this generally will make design easier to write, read, and debug. The calc process is an example of a process both updating on rising edge of clk and on calcstate.