串行线上的MQTT-SN（蓝牙，CAN，RS485，...）(MQTT-SN over Serial Wire (Bluetooth, CAN, RS485, …))

 你的链式信号向后，第一个输入要显示相等： 
 
architecture comp32_arch of comp32 is
  component comp1
  port (a,b,g,l,e : in std_logic ;
       great,less,equal : out std_logic);   
  end component comp1;

  signal gre : std_logic_vector(BW downto 0);
  signal les : std_logic_vector(BW downto 0);
  signal equ : std_logic_vector(BW downto 0);

  begin
      gre(BW) <= '0';   -- gre(0) <= '0';
      les(BW) <= '0';   -- les(0) <= '0';
      equ(BW) <= '1';   -- equ(0) <= '0';

  gen: 
      for i in 0 to BW-1 generate
  biti:
          comp1 
              port map ( 
                  a => a_32(i),
                  b => b_32(i),
                  g => gre(i+1),   -- gre(i),
                  l => les(i+1),   -- les(i), 
                  e => equ(i+1),   -- equ(i), 
                  great => gre(i), -- gre(i+1), 
                  less => les(i),  -- les(i+1), 
                  equal => equ(i)  -- equ(i+1)
              );
          end generate;
      g_32 <= gre(0);  -- gre(BW);-- (BW-1);
      l_32 <= les(0);  -- les(BW); -- (BW-1);          
      e_32 <= equ(0);  -- equ(BW); -- (BW-1);  
end architecture comp32_arch;
 
 这给了： 
 
  
 
 没有等于的最重要的位定义小于或大于。 如果他们都是平等的，那么一直传播。 

You had your chained signals backward, and the first inputs want to show equal:
 
architecture comp32_arch of comp32 is
  component comp1
  port (a,b,g,l,e : in std_logic ;
       great,less,equal : out std_logic);   
  end component comp1;

  signal gre : std_logic_vector(BW downto 0);
  signal les : std_logic_vector(BW downto 0);
  signal equ : std_logic_vector(BW downto 0);

  begin
      gre(BW) <= '0';   -- gre(0) <= '0';
      les(BW) <= '0';   -- les(0) <= '0';
      equ(BW) <= '1';   -- equ(0) <= '0';

  gen: 
      for i in 0 to BW-1 generate
  biti:
          comp1 
              port map ( 
                  a => a_32(i),
                  b => b_32(i),
                  g => gre(i+1),   -- gre(i),
                  l => les(i+1),   -- les(i), 
                  e => equ(i+1),   -- equ(i), 
                  great => gre(i), -- gre(i+1), 
                  less => les(i),  -- les(i+1), 
                  equal => equ(i)  -- equ(i+1)
              );
          end generate;
      g_32 <= gre(0);  -- gre(BW);-- (BW-1);
      l_32 <= les(0);  -- les(BW); -- (BW-1);          
      e_32 <= equ(0);  -- equ(BW); -- (BW-1);  
end architecture comp32_arch;
 
And that gives:
 
 
The most significant bit without an equals defines either less than or greater than. If they're all equal that propagates all the way through.