是否可以在vhdl中使用泛型类型？(Is it possible to have generic type in vhdl?)

 VHDL中有没有一种方法可以使用泛型类型？ 所以例如我想调用一个过程，但是我不确定我想要作为参数给出的信号类型，是否可以将参数声明为通用？ 就像在C ++中一样，你会使用一个模板。 
 
procedure eq_checker(name : string; sig : ANYTHING); should : ANYTHING; at : time) is
  if (at = now) then
    if sig = should then
      report "has same value" severity note;
    else
      report "has not same value" severity note;
    end if;
  end if;
end checker;
 
 至少应该可以使用不同的信号类型作为“sig”。 

Is there a way in VHDL to have generic types? So for example I want to call a procedure but I'm not sure what type the signal has I want to give as paarameter, is it possible to declare the parameter as generic? Like in C++ you would use a Template.
 
procedure eq_checker(name : string; sig : ANYTHING); should : ANYTHING; at : time) is
  if (at = now) then
    if sig = should then
      report "has same value" severity note;
    else
      report "has not same value" severity note;
    end if;
  end if;
end checker;
 
At least it should be possible to use different signal types as "sig".

原文：https://stackoverflow.com/questions/15382791