我在verilog上以4：1的形式进行多路复用，但输出并不是经过考验的(I am doing a mux 4:1 on verilog, but the output is not the expeted)

 我在互联网上看到了一些关于verilog的mux 4：1的例子。 我试图做一些事情，但输出不是被开除的。 这是来源： 
 
module mux41 (a, b, c, d,select,z);

input a,b,c,d;
input [1:0]select;
output reg z;

always@(select )
begin
case (select)
    2'b00: assign z=a;
    2'b01: assign z=b;
    2'b10: assign z=c;
    2'b11: assign z=d;
endcase
end
endmodule
 
 这是测试平台： 
 
module mux41_tb;

reg at,bt,ct,dt;
reg [1:0] selectt;
wire zt;

mux41   test(.a(at),.b(bt),.c(ct),.d(dt),.select(selectt),
            .z(zt));

initial
begin
     $monitor ("a=%d",at,"b=%b",bt,"c=%b",ct,
                    "d=%b","select=%b",selectt,"z=%z",zt);

    selectt =2'b00;
    #5
    selectt =2'b01;
    #5
    selectt =2'b10;
    #5
    selectt =2'b11;
    #5;

end

endmodule
 
 但输出如下： 
 
  
 
 我的问题是我在两个代码（源代码和测试平台）中应该有什么机会。 
 
 丁基，NIN。 

I've seen some examples on internet about mux 4:1 on verilog. I've tried to do something but the output is not the expeted. This is the source :
 
module mux41 (a, b, c, d,select,z);

input a,b,c,d;
input [1:0]select;
output reg z;

always@(select )
begin
case (select)
    2'b00: assign z=a;
    2'b01: assign z=b;
    2'b10: assign z=c;
    2'b11: assign z=d;
endcase
end
endmodule
 
and this is the testbench :
 
module mux41_tb;

reg at,bt,ct,dt;
reg [1:0] selectt;
wire zt;

mux41   test(.a(at),.b(bt),.c(ct),.d(dt),.select(selectt),
            .z(zt));

initial
begin
     $monitor ("a=%d",at,"b=%b",bt,"c=%b",ct,
                    "d=%b","select=%b",selectt,"z=%z",zt);

    selectt =2'b00;
    #5
    selectt =2'b01;
    #5
    selectt =2'b10;
    #5
    selectt =2'b11;
    #5;

end

endmodule
 
but the output is the following :
 
 
My question is what I should chance in both codes (source and testbench).
 
Sincerylly, NIN.

原文：https://stackoverflow.com/questions/39129028