在MIPS中使用SW和LW访问代码段内存(Accessing code segment memory using SW and LW in MIPS)

 考虑到指令的地址，是否可以使用MIPS中的SW和LW指令访问代码段存储器？ 
 
 例如： 
 
0x1000: ADDI $s1, $zero, 0x1000
0x1004: LW $s2, 4($s1)
 
 代码将加载到$s2 ？ 0x0000 （假定数据段为空）或0x1004指令的二进制表示？ 
 
 编辑： 
 
 AFAIK，MIPS处理器中的流水线操作可能是由于指令存储器和数据存储器的分离 - 如果我错了，请纠正我。 
 
 编辑2： 
 
 我发现了一个问题 ，其答案意味着可以使用LW和SW访问和修改指令。 因此，答案是$s2将包含指令在0x1004的二进制表示。 

Is it possible to access the code segment memory using the SW and LW instructions in MIPS, given the address of the instructions?
 
For example:
 
0x1000: ADDI $s1, $zero, 0x1000
0x1004: LW $s2, 4($s1)
 
What would the code load into $s2? 0x0000 (given the data segment is empty) or binary representation of the instruction at 0x1004?
 
EDIT:
 
AFAIK, pipelining in MIPS processor is possible due to separation of the instructions memory and the data memory - correct me if I'm wrong.
 
EDIT 2:
 
I've found a question, the answer to which implies that the instructions can be accessed and modified using LW and SW. Thus the answer is $s2 will contain the binary representation of the instruction at 0x1004.

原文：https://stackoverflow.com/questions/47971462